Liquid crystal displays (LCDs) have been widely applied in electronic products, such as digital watches and calculators, for a long time. With the advance of techniques for manufacture and design, the thin film transistor liquid crystal displays (TFT-LCDs) have been introduced into portable computers, personal digital assistants and color televisions, and have gradually replaced the kinescopes that are used for conventional displays. However, consequent of the TFT-LCD design rules trend toward large scale, there are a lot of problems and challenges, such as low yields and low throughput, in manufacturing and developing TFT-LCD apparatuses.
In general, the TFT-LCD comprises a bottom plate on which thin film transistors and pixel electrodes are formed, and a top plate on which color filters are constructed. The liquid crystal molecules are filled between the top plate and the bottom plate. During operation, a signal voltage is applied to the TFT, which is the switching element of each pixel unit. The TFT receives the signal voltage and it turns on so that data voltage carrying image information can be applied to the corresponding pixel electrode and the liquid crystal via the TFT. When the data voltage is applied to the TFT, the orientation of the liquid crystal molecules is changed, thereby altering the optical properties and displaying the image. Generally, the voltage applied to the pixel electrode is from the signal line coupled to the corresponding TFT that is switched by the voltage from the gate line.
There is an ongoing requirement to reduce the photolithography processes in manufacturing TFT devices in order to decrease the process cycle time and cost. Namely, it is better to reduce the number of photomasks used in forming the TFT devices.
According to the prior art of concurrently manufacturing the thin film transistor and the peripheral CMOS transistor (Complementary Metal-Oxide Semiconductor) control circuit for a reflection type or transmission type TFT-LCD, eight or more photomasks are needed. The cost incurred by employing this conventional manufacturing method is thus significant and its reduction is required for a manufacturer to remain competitive.
FIG. 1 illustrates the structure of the thin film transistor 200 and the peripheral CMOS control circuit 202 that are formed over a glass substrate 100 according to the conventional method. First, a polycrystalline thin film is deposited over a glass substrate 100 to define the location and scale of active region structures 101, 102 and 103 of the thin film transistor 200 and the peripheral CMOS transistor control circuit 202, wherein the active region structures 102 and 103 are respectively used to form the PMOS (P-type Metal-Oxide Semiconductor) transistor and the NMOS (N-type Metal-Oxide Semiconductor) transistor of the CMOS transistor. An insulating layer 104 is formed on the glass substrate 100 to cover the active region structures 101, 102 and 103. A gate structure 106 is formed above the insulating layer 104 and the active region structures 101, 102 and 103. Next, an ion implanting step is performed to form the N+ doped polysilicon layer 108 in the active region structures 101 and 102. Another ion implanting step is performed to form the P+ doped polysilicon layer 110 in the active region structure 103. A step for forming the lightly doped drain (LDD) region 124 may be performed before the step of forming the N+ doped polysilicon layer 108. Then, an ILD (interlayer dielectric) layer 112 is formed over the insulating layer 104. An etching step is performed to form the via and contact window and fill them with a metal to act as the source/drain electrode 114. A passivation layer 116 is deposited over the ILD layer 112, which has a contact hole to expose the surface of the source/drain electrode 114. Then, an indium tin oxide (ITO) layer 122 is deposited on the passivation layer 116 to form the pixel electrode and connect to the source/drain electrode 114. Finally, an electrical connection is made between the thin film transistor 200 and the peripheral CMOS control circuit 202.
It is noted that the TFT device 200 and the peripheral CMOS transistor control circuit 202 as illustrated in FIG. 1 are manufactured by using nine photomasks. The first photomask is used to define the active region structures 101, 102 and 103. The second photomask is used to define the gate structure 106. The third photomask is used to define the NMOS transistor region of the peripheral CMOS transistor control circuit 202 and the TFT regions. The lightly doped drain (LDD) region 124 is also defined in this step. The fourth photomask is used to define the N+ doped polysilicon layer 108. The fifth photomask is used to define the PMOS transistor region of the peripheral CMOS transistor control circuit 202. The P+ doped polysilicon layer 110 is also defined in this step. The sixth photomask is used to define the via of the ILD layer 112. The seventh photomask is used to define the pattern of the source/drain electrode 114. The eighth photomask is used to define the contact hole 120 of the passivation layer 116. The ninth photomask is used to define the pattern of the ITO layer 122. Although the TFT device 200 and the peripheral CMOS transistor control circuit 202 as illustrated in FIG. 1 may be manufactured by using these nine photomasks, much process cycle time and cost are incurred.